The invention is directed to non-volatile memories. More specifically, the invention is directed to one-time programmable (OTP) memory cells and memory devices.
Anti-fuse memory is one type of one-time programmable (OTP) memory in which the device can be permanently programmed (electrically) with data once. This data is programmed by an end user for a particular application. There are several types of OTP memory cells which can be used. OTP memories provide users with a level of flexibility since any data can be programmed.
Anti-fuse memory can be utilized in one-time programmable applications where it is desired to provide pre-programmed information to a system, in which the information cannot be modified. One example application includes radio frequency identification (RF-ID) tags. RF-ID tagging applications are gaining more acceptance in the industry, particularly in sales, security, transport, logistics, and military applications for example. The simplicity and full complementary metal-oxide-semiconductor (CMOS) compatibility of anti-fuse memory allows for application of the RF-ID tag concept to integrated circuit manufacturing and testing processes.
FIG. 1A is a circuit diagram illustrating the basic concept of an anti-fuse memory cell, while FIGS. 1B and 1C show the planar and cross-sectional views respectively, of the anti-fuse memory cell shown in FIG. 1. The memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12. This cell is also referred to as a 1.5-transistor (1.5T) cell. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage CL (program/read control line) is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
It can be seen from FIGS. 1B and 1C that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of material, such as polysilicon or metal, which extend across active area 18. In the active area 18 underneath each gate is formed a thin gate oxide 20 (or gate dielectric), for electrically isolating the gate from the active area underneath. The thin gate oxide 20 can be the same thickness underneath both gates 14 and 16, or can be made thicker under gate 14. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard CMOS processing, such as sidewall spacer formation, lightly doped drains (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses must be reliable while simple to manufacture with a low-cost CMOS process.
FIG. 2A shows a cross-sectional view of an anti-fuse transistor that can be manufactured with any standard CMOS process. Variants of this anti-fuse transistor are described in U.S. patent application Ser. No. 11/762,552, filed on Jun. 13, 2007, now issued as U.S. Pat. No. 7,755,162, the contents of which are incorporated by reference. In the presently shown example, the anti-fuse transistor is almost identical to a simple thick gate oxide, or input/output metal oxide semiconductor (MOS) transistor. The disclosed anti-fuse transistor, also termed a split-channel capacitor or a split-channel transistor, can be reliably programmed such that the fuse link between the polysilicon gate and the substrate can be predictably localized to a particular region of the device. The cross-section view of FIG. 2A is taken along the channel length of the device, which in the presently described example is a p-channel device.
Anti-fuse transistor 26 includes a variable thickness gate oxide 28 formed on the substrate channel region 30, a polysilicon or metal gate 32, sidewall spacers 34, a field oxide region 36 such as shallow trench isolation for example, a diffusion region 38 and a LDD region 40 in the diffusion region 38. LDD region 40 is a high voltage LDD, meaning that it is formed using whatever process parameters are used for forming high voltage transistors and corresponding diffusion regions and LDDs. A bitline contact 42 is shown to be in electrical contact with diffusion region 38. The variable thickness gate oxide 28 includes a thick oxide and a thin gate oxide such that a portion of the channel length is covered by the thick gate oxide and the remaining portion of the channel length is covered by the thin gate oxide. Generally, the thin gate oxide is a region where oxide breakdown can occur, and forms the anti-fuse device portion of anti-fuse transistor 26 that functions as anti-fuse device 12 of the cell of FIG. 1B. The thicker portion of variable thickness gate oxide 28 forms the access transistor portion of anti-fuse transistor 26 that functions as access transistor 10 of the cell of FIG. 1B. This cell is also referred to as a 1 transistor (1T) cell. The thick gate oxide edge meeting diffusion region 38 on the other hand, defines an access edge where gate oxide breakdown is prevented and current between the gate 32 and diffusion region 38 is to flow for a programmed anti-fuse transistor. While the distance that the thick oxide portion extends into the channel region depends on the mask grade, the thick oxide portion is preferably formed to be at least as long as the minimum length of a high voltage transistor formed on the same chip.
In this example, the diffusion region 38 is connected to a bitline through a bitline contact 42, or other line for sensing a current from the polysilicon gate 32, and can be doped to accommodate programming voltages or currents. This diffusion region 38 is formed proximate to the thick oxide portion of the variable thickness gate oxide 28. Diffusion region 38 can be doped for low voltage transistors or high voltage transistors or a combination of the two resulting in same or different diffusion profiles.
A simplified plan view of the anti-fuse transistor 26 is shown in FIG. 2B. Bitline contact 42 can be used as a visual reference point to orient the plan view with the corresponding cross-sectional view of FIG. 2A. The active area 44 is the region of the device where the channel region 30 and diffusion region 38 are formed, which is defined by an OD (oxide diffusion) mask during the fabrication process. The dashed outline 46 defines the areas in which the thick gate oxide is to be formed via a second oxide diffusion (OD2) mask during the fabrication process. More specifically, the area enclosed by the dashed outline 46 designates the regions where thick oxide is to be formed. An oxide definition mask (or Active Area), is used during the CMOS process for defining the regions on the substrate where the oxide is to be formed. An OD2 mask refers to a second oxide definition mask different than the first (Dual Gate, or Thick Gate oxide mask). Details of the CMOS process steps for fabricating anti-fuse transistor 26 are discussed in previously mentioned U.S. Pat. No. 7,755,162. In one embodiment, the thin gate oxide area bounded by edges of the active area 44 and the rightmost edge of the OD2 mask is minimized. In the presently shown embodiment, this area can be minimized by shifting the rightmost OD2 mask edge towards the parallel edge of active area 44. Previously mentioned U.S. Pat. No. 7,755,162 describes alternate single transistor anti-fuse memory cells which can be used in a non-volatile memory array.
FIG. 2C is a circuit diagram symbol representing anti-fuse transistor 26 of FIGS. 2A and 2B, with annotations showing the connections to a wordline WL and a bitline BL when used in a memory array.
Memories such as OTP memory are used in an increasing number of mobile devices, including smart phones, wearable technologies and other electronic devices that make up the Internet of Things (IoT). Unfortunately, mobile devices have a finite power supply which is consumed quickly as more functionality is added to them. Accordingly, all semiconductor devices of mobile devices should consume a minimum amount of power, and OTP memory are no exception. This lower power requirement of device manufacturers manifests primarily in the form of lowering the operating voltage of the OTP memory device. Furthermore, wearable devices are intended to be small, therefore the area of the OTP memory should be reduced as well in order to facilitate integration with other devices of the mobile system. Not only should the devices use low power and be small in size, they must also operate reliably. For example, the OTP memory should accurately store the data intended to be programmed to it.
Previously implemented memory devices utilizing the anti-fuse memory cells shown in FIGS. 1A-1C and 2A-2C have efficient memory arrays, meaning that the area occupied by the memory array is small when compared to the number of bits the memory array can store. However, high voltages are required to program an anti-fuse memory cell. Therefore, a large proportion of the memory device chip, or instance/macro if embedded in a larger system, is occupied by level shifters and high voltage transistors which have large dimensions relative to low voltage core logic transistors.